1. Field of the Invention
The present invention relates to a binary conversion circuit and method that can be applied to a solid-state imaging device represented by a CMOS image sensor, an analog-to-digital (AD) converter, a solid-state imaging device, and a camera system.
2. Description of the Related Art
Hitherto, in the field of image sensors, a structure has been proposed in which a comparator that compares a pixel output and a ramp-shaped reference potential with each other and a ripple counter for measuring the time elapsed until the pixel output and the reference potential cross each other are provided for each column. Such a structure is disclosed in JP-A-2006-033453 and JP-A-2005-278135, for example.
FIG. 1 is a diagram showing a typical circuit example that has a comparator and a counter.
FIG. 2 is a timing chart of the circuit in FIG. 1.
In this circuit, a count operation of a counter 2 is started when a comparator 1 starts sweeping a reference voltage Vramp.
When the reference voltage Vramp is lower than an input voltage VSL, an output signal VCO of the comparator 1 is inverted from a high level to a low level, and the count operation of the counter 2 is stopped at this falling edge.
A count value VCNT is in one-to-one correspondence to a voltage width that the reference voltage Vramp has swept, and the count value VCNT reflects an analog-to-digital (AD) conversion result for the input voltage.
In JP-A-2006-033453 and JP-A-2005-278135, a ripple counter is used as the counter, and a subtraction operation is realized by inverting each bit of the ripple counter.
Moreover, an addition operation is realized by continuously operating the ripple counter with subsequent data while holding the count value for the first data.
According to this configuration, since a CDS (Correlated Double Sampling) operation which is frequently performed in an image sensor is performed individually in each column, an AD conversion result of a pixel output does not depend on an inter-column clock skew or a reference potential skew.
As a consequence, a count operation based on a high-frequency clock is possible. Moreover, since the AD conversion results are added or subtracted in units of columns, it is advantageous in that an addition operation of the pixel output in the same column can be performed on an AD converter circuit.